1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a refresh circuit.
2. Related Art
A semiconductor memory apparatus, as an apparatus that stores data, must perform an operation of holding and storing the data. The operation of holding and storing the data, which is performed by the semiconductor memory apparatus is referred to as a refresh operation.
The semiconductor memory apparatus does not activate all banks at once in order to reduce peak current at the time of performing the refresh operation. For example, on the basis of 8 banks, a refresh scheme includes a scheme in which 4 banks are activated at one time (2 piled refresh), a scheme in which 2 banks are activated at one time (4 piled refresh), etc.
As shown in FIG. 1, the general refresh circuit can be configured to include a bank active signal generator 10 and a precharge pulse generator 20. The semiconductor memory apparatus having 8 banks is described as one example.
The bank active signal generator 10 can generate first to eighth bank active signals ‘BA<0:7>’ in response to a refresh signal ‘REF’ and a piled signal ‘T2PILE’. For example, when the refresh signal ‘REF’ and the piled signal ‘T2PILE’ are enabled, the bank active signal generator 10 firstly enables the second, fourth, fifth, and seventh bank active signals ‘BA<1>’, ‘BA<3>’, ‘BA<4>’, and ‘BA<6>’ and thereafter, enables the first, third, sixth, and eighth bank active signals ‘BA<0>’, ‘BA<2>’, ‘BA<5>’, and ‘BA<7>’, among the first to eighth bank active signals ‘BA<0:7>’.
Further, when the refresh signal ‘REF’ is enabled and the piled signal ‘T2PILE’ is disabled, the bank active signal generator 10 firstly enables the fourth and fifth bank active signals ‘BA<3>’ and ‘BA<4>’, secondly enables the third and sixth bank active signals ‘BA<2>’ and ‘BA<5>’, thirdly enables the second and seventh bank active signals ‘BA<1>’ and ‘BA<6>’, and lastly enables the first and eighth bank active signals ‘BA<0>’ and ‘BA<7>’, among the first to eighth bank active signals ‘BA<0>’ to ‘BA<7>’. Further, when first to eighth precharge pulses ‘pre_pulse<0:7>’ are inputted, the bank active signal generator 10 disables the corresponding bank active signals ‘BA<0:7>’. For example, when the first precharge pulse ‘pre_pulse<0>’ is inputted, the bank active signal generator 10 disables the first bank active signal ‘BA<0>’.
The precharge pulse generator 20 generates each of the first to eighth precharge pulses ‘pre_pulse<0:7>’ after a set time from the time when each of the first to eighth bank active signals ‘BA<0:7>’ is enabled.
The general refresh circuit is configured to disable the bank active signal after the set time when the bank active signal is enabled. The refresh circuit operates in the 4 piled refresh scheme in which the refresh operation is performed by activating each of 2 banks among 8 banks or the 2 piled refresh scheme in which the refresh operation is performed by activating each of 4 banks. At this time, the 4 piled refresh scheme in which each of 2 banks among 8 banks is activated has a refresh operation time longer than the 2 piled refresh scheme in which each of 4 banks among 8 banks is activated. The reason for this is that in the 4 piled refresh scheme and the 2 piled refresh scheme, other bank groups are activated when the same time elapses after one-bank groups are activated.
When the semiconductor memory apparatus performs the refresh operation, the longer the activation time of the bank is, the better a refresh characteristic is. However, in the case of the general refresh circuit, the 4 piled refresh scheme has the operation time longer than the 2 piled refresh scheme, while the 4 piled refresh scheme has the same activation time of each bank as the 2 piled refresh scheme. Since the refresh operation time of the semiconductor memory apparatus must be determined on the basis of the standards of the Joint Electron Device Engineering Council (JEDEC), the refresh operation time of the known semiconductor memory apparatus according to the 4 piled refresh scheme having the operation time longer than the 2 piled refresh scheme is designed to suit the standards of the JEDEC. Therefore, the known 2 piled refresh scheme has been adopted with a refresh operation time shorter than the standards of the JEDEC.